Intel MIC to power 10 PF super at TACC

Although the Intel MIC platform (Knights Ferry and co) will not be ready until the end of next year, it seems that Intel already scoared a big goal having been selected to power an upcoming 10PF supercomputer at TACC. The full system will provide 2 petaflops of Sandy Bridge-EP processors and 8 petaflops of Intel's Many Integrated Core coprocessors. The MIC coprocessors will apparently be preproduction Knights Corner chips. The system also means the first searious blow to NVIDIA/AMD in the accelerated computing sector. Intel's MIC chips are based on the Intel64 instruction set and are compatible with popular programming models such as OpenMP which provides a much easier transition path for legacy codes. It seems that these first generation chips will include above 50 cores connected by a ring and with high bandwidth external memory (note Larrabee legacy here). The GPGPU community has so far not taken the Intel MIC line as a serious threat, mainly (I guess) because the chips are entering this market segment quite late. The CUDA programming model enforces programming methodologies that are very interesting for particularly regular applications (i.e., those that can efficiently exploit the SM shared memories). MIC may not have the computing density to beat NVIDIA on these apps, but it may well surpass the performance on irregular apps such as those dealing with unstructured grids, graphs or other sparse and pointer-based data structures thanks to its large L2 and less strict programming model. And in my view such apps will play an increasingly important role in the future. It will be an interesting battle to watch.

More information on TACC's Stampede supercomputer can be found here.